View ISL59451IRZ_4166344.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
ISL59451
Data Sheet September 24, 2007 FN6253.0
Triple 4:1 DC Restored Single Supply Video Multiplexing Amplifier
The ISL59451 is a 4-input, single-supply triple video multiplexer. It features a DC restore function that makes it ideally suited for single-supply AC-coupled component video applications where amplifier headroom is a concern. When logic "0" is applied to CLAMP, the sample-hold amplifier loop is closed and the DC level of the amplifier output is set to the corresponding reference level. This can occur during sync, or at any time that a black level is expected. When logic "1" is applied to CLAMP, the clamp is disabled and the correcting voltage is stored on each video amplifier's input coupling capacitor. This DC reference condition is maintained during the active video period. The restored DC voltage level can be adjusted over a range of 0V to +3V using external reference voltages applied to the REF_G and REF_RB pins. The device features a TTL/CMOS logic compatible gain select pin (AV2) of x1 or x2. When HIZ is pulled high, the outputs are put into high-impedance states and the video inputs are disconnected. This is an essential feature for power sensitive applications. The ISL59451 also features channel-switching at pixel rates to allow for video overlays. The ISL59451 operates from a single +5V supply and is ideal for +5V systems when used with sync separators such as the EL1883. The red and blue channels share a common reference pin (REF_RB) which can also be used to adjust chroma offsets in YPbPr systems. The green channel has a separate reference pin (REF_G), which can be used to accommodate sync-on-green or luma. The ISL59451 is comes in a 32 Ld QFN package and is specified for operation over the -40C to +85C extended temperature range.
Features
* Complete Video Level DC Restoration System * 250MHz Bandwidth (GAIN = 1) * +5V Single Supply Operation * Capable of Pixel Rate Channel Switching * TTL/CMOS Compatible Keyed Clamp Control * High Impedance Output Setting * 150 Output Load Capability for Video Cable Driving * Ideal for RGB/YPbPr/S-Video/Composite Video Signals * Pb-Free (RoHS Compliant)
Applications
* SDTVs and HDTVs * Set-Top Boxes * Video Overlay * Security Video * Broadcast Video Equipment
Pinout
ISL59451 (32 LD QFN) TOP VIEW
32 GND 27 GND 25 AV2 24 ROUT 23 REF_RB
2/1
R1 1 B1 2 G1 3
THERMAL PAD
2/1
26 HIZ
28 V+
31 G0
30 B0
29 R0
22 GND 21 BOUT 20 V+
Ordering Information
PART NUMBER (Note) ISL59451IRZ ISL59451IRZ-T7* PART MARKING PACKAGE (Pb-Free) PKG. DWG. # L32.5x5 L32.5x5
GND 4 V+ 5
2/1
ISL594 51IRZ 32 Ld 5x5 QFN ISL594 51IRZ 32 Ld 5x5 QFN
GND 6 R2 7 B2 8 GND 10 R3 11 B3 12 G3 13 S1 14 S0 15 CLAMP 16 G2 9
19 REF_G 18 GOUT 17 GND
*Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Exposed Thermal Pad (Gray Area) must be connected to GND.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2007. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL59451
Absolute Maximum Ratings (TA = +25C)
Supply Voltage (V+ to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Input Voltage to GND. . . . . . . . . . . . . . . . . .GND - 0.5V to V+ +0.5V Voltage between HIZ, CLAMP, AV2, REF_ and GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.5;V+ +0.5V Supply Turn-on Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/s Digital and Analog Input Current (Note 1) . . . . . . . . . . . . . . . . 50mA Output Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7). . . .2500V Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V
Thermal Information
Storage Temperature Range . . . . . . . . . . . . . . . . . . -65C to +150C Ambient Operating Temperature . . . . . . . . . . . . . . . . -40C to +85C Operating Junction Temperature . . . . . . . . . . . . . . . -40C to +125C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Curves Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTE: 1. If an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values. 2. Parts are 100% tested at +25C. Over-temperature limits established by characterization and are not production tested.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
V+ = +5V, GND = 0V, TA = +25C, RL = 150 to GND, REF_G = 0.5V, REF_RB = 1.2V, CLAMP = 2.0V, S1 = S0 = AV2 = HIZ = 0.8V, unless otherwise specified. CONDITIONS MIN (Note 2) TYP MAX (Note 2) UNIT
PARAMETER DC CHARACTERISTICS V+ +IS Enabled +IS Disabled VSHIFT IB ROUT_DIS AV
DESCRIPTION
Supply Voltage Enabled Supply Current Disabled Supply Current No load, VIN = 2.2V, HIZ = 0.8V No load, VIN = 2.2V, HIZ = 2.0V
4.5
5.0 45 3
5.5 75 5 2 1 2.6 1.02 2.05
V mA mA V A k V/V V/V dB dB
Input to Output Level Shift (VIN - VOUT) DC-coupled inputs, VIN = 2V, GAIN = 1 Input Bias Current Disabled Output Resistance (DC) Voltage Gain VIN = 2.2V, No Load HIZ = 2.0V AV2 = 0.8V, GAIN = 1 AV2 = 2.0V, GAIN = 2
1.2 -1 1.4 0.98 1.95 40 50
1.6 0 2 1 2.00 50 65
PSRRDC
DC Power Supply Rejection Ratio
V+ = 4.5V to 5.5V, CLAMP = 2.0V, VIN = 2.0V V+ = 4.5V to 5.5V, CLAMP = 0.8V, inputs floating
OUTPUT AMPLIFIERS VOUT+ VOUTISC Maximum Output High Level Minimum Output Low Level Short Circuit Current RL = 150, VIN = 4V, GAIN = 2 RL = 150,VIN = 0.8V, GAIN = 2 Sourcing, VIN = 4V, RL = 10 to GND, GAIN = 2 Sinking, VIN = 0V, RL = 10 to +3V DC RESTORE SECTION VCLAMP-OS Output Clamp Accuracy (VOUT VREF_RB) REF_RB = 1.2V, CLAMP = 0.8V -15 -15 500 150 -2 -3 -4 -3 860 290 -0.4 -0.9 +10 +10 1100 500 +0.5 +0.5 mV mV A A A A 125 57 3.5 15 V mV mA mA
Output Clamp Accuracy (VOUT - VREF_G) REF_G = 0.5V, CLAMP = 0.8V ICLAMP Positive Restore Clamp Current Negative Restore Clamp Current IB_VREF Reference Input Bias Current VIN = 0V, CLAMP = 0.8V, Sourcing VIN = 4V, CLAMP = 0.8V, Sinking REF_G = 0.5V or 1.2V, VCLAMP = 0.8V REF_RB = 0.5V or 1.2V, VCLAMP = 0.8V
2
FN6253.0 September 24, 2007
ISL59451
Electrical Specifications
V+ = +5V, GND = 0V, TA = +25C, RL = 150 to GND, REF_G = 0.5V, REF_RB = 1.2V, CLAMP = 2.0V, S1 = S0 = AV2 = HIZ = 0.8V, unless otherwise specified. (Continued) CONDITIONS MIN (Note 2) TYP MAX (Note 2) UNIT
PARAMETER
DESCRIPTION
LOGIC (CLAMP, AV2, HIZ, S1, S0) VIH VIL IIH Input High Voltage (HIGH) Input Low Voltage (LOW) Input High Current (Logic Inputs) S1 = S0 = CLAMP = 5V (no pull-up or pull-down) AV2 = HIZ= 5V (300k internal pull-downs) IIL Input Low Current (Logic Inputs) S1 = S0 = CLAMP = 0V (no pull-up or pull-down) AV2 = HIZ= 5V (300k internal pull-downs) AC GENERAL PSRR XTALK Power Supply Rejection Ratio Channel-to-Channel Crosstalk (ROUT/BOUT to Green Input) VIN = 2.0V, f = 10kHz to 10MHz, V+ = 5VDC + 100mVP-P sine wave f = 10MHz, VIN = 0.7VP-P; (GAIN = 1) f = 10MHz, VIN = 0.7VP-P; (GAIN = 2) 50 60 55 94 89 0.0025 0.08 240 200 210 200 30 30 500 930 300 600 dB dB dB dB dB % MHz MHz MHz MHz MHz MHz V/s V/s V/s V/s -1 8 -1 -1 0 17 0 0 2 0.8 +1 34 +1 +1 V V A A A A
OFFCH_ISO
De-Selected Channel Isolation f = 10MHz, Ch-Ch Off Isolation (any de-selected output to driven input) VIN = 0.7VP-P; (GAIN = 1) f = 10MHz, Ch-Ch Off Isolation VIN = 0.7VP-P; (GAIN = 2)
dG dP BW
Differential Gain Error Differential Phase Error Small Signal -3dB Bandwidth
RL = 150 RL = 150 VOUT = 0.2VP-P; RL = 150, CL = 0.6pF (GAIN = 1) VOUT = 0.2VP-P; RL = 150, CL = 0.6pF (GAIN = 2)
Large Signal -3dB Bandwidth
VOUT = 1.4VP-P; RL = 150, CL = 0.6pF (GAIN = 1) VOUT = 1.4VP-P; RL = 150, CL = 0.6pF (GAIN = 2)
BW_0.1
0.1dB Bandwidth
VOUT = 1.4VP-P; RL = 150, CL = 0.6pF (GAIN = 1) VOUT = 1.4VP-P; RL = 150, CL = 0.6pF (GAIN = 2)
SR+
Positive Slew Rate
VIN = 1.8 to 2.8V, time = 10% to 90%, RL = 150, GAIN = 1 VIN = 1.8 to 2.3V, time = 10% to 90%, RL = 150, GAIN = 2
SR-
Negative Slew Rate
VIN = 2.8 to 1.8V, time = 90% to 10%, RL = 150, GAIN = 1 VIN = 2.3 to 1.8V, time = 90% to 10%, RL = 150, GAIN = 2
TRANSIENT RESPONSE tR Rise Time 10% to 90% Fall Time 90% to 10% Settling Time to 1% VOUT = 0.7VP-P; RL = 150, CL = 2.1pF, GAIN = 1 VOUT = 1.4VP-P; RL = 150, CL = 2.1pF, GAIN = 2 VOUT = 0.7VP-P; RL = 150, CL = 2.1pF, GAIN = 1 VOUT = 1.4VP-P; RL = 150, CL = 2.1pF, GAIN = 2 VOUT = 1VP-P; RL = 150, CL = 2.1pF, GAIN = 1, time from 90% crossing to 1% of final value VOUT = 1VP-P; RL = 150, CL = 2.1pF, GAIN = 2, time from 90% crossing to 1% of final value 1.3 2 2.6 2.3 2 4 ns ns ns ns ns ns
tF
tS 1%
3
FN6253.0 September 24, 2007
ISL59451
Electrical Specifications
V+ = +5V, GND = 0V, TA = +25C, RL = 150 to GND, REF_G = 0.5V, REF_RB = 1.2V, CLAMP = 2.0V, S1 = S0 = AV2 = HIZ = 0.8V, unless otherwise specified. (Continued) CONDITIONS MIN (Note 2) TYP MAX (Note 2) UNIT
PARAMETER
DESCRIPTION
SWITCHING CHARACTERISTICS VGLITCH HIZ High to Low Switching Glitch VIN = 1V, RL = 150; CL = 2.1pF, GAIN = 1 VIN = 1V, RL = 150; CL = 2.1pF, GAIN = 2 tSW-L-H tSW-H-L tHIZ-L-H tHIZ-H-L tpd tHE tHD Channel Switching Delay Time Low to High Channel Switching Delay Time High to Low HIZ Switching Delay Time Low to High HIZ Switching Delay Time High to Low Propagation Delay Time to Enable CLAMP Time to Disable CLAMP 1.2V logic threshold to 10% movement of analog output 1.2V logic threshold to 10% movement of analog output 1.2V logic threshold to 10% movement of analog output 1.2V logic threshold to 10% movement of analog output 10% input to 10% output CLAMP = LOW to settled output CLAMP = HIGH to settled output 500 300 3 4 25 220 2.5 40 20 mVP-P mVP-P ns ns ns ns ns ns ns
Settling Time Diagram
1% OF FINAL VALUE BAND FINAL VALUE 90% FINAL VALUE
10% FINAL VALUE tR tS 1%
4
FN6253.0 September 24, 2007
ISL59451 Typical Application Circuit
+5V
1nF C
10nF
1F
RED/Pr
0.1F R0 75
S1
S0
AV2
V+
GREEN/Y
0.1F G0 75
3
BLUE/Pb
0.1F B0 75 CLAMP R1 75 1.6VDC 0.1F 75 G1 + 00 B1 75 01 10 R2 75 11 + G2 75 3 S1, S0 X1/ X2 1.6VDC BOUT 75 BLUE/Pb REF_RB 1.6VDC X1/ X2 75 GOUT GREEN/Y 3 REF_G X1/ X2 75 ROUT VIDEO OUT RED/Pr + REF_RB
RED/Pr
0.1F
GREEN/Y
BLUE/Pb
0.1F
RED/Pr
0.1F
VIDEO OUT
GREEN/Y
0.1F
BLUE/Pb
0.1F B2 75
VIDEO OUT
RED/Pr
0.1F R3 75
GREEN/Y
0.1F G3 75
3
BLUE/Pb
0.1F B3 75 REF_G REF_RB CLAMP
ISL59451
HIZ GND PULSE 0.5V 1.2V
5
FN6253.0 September 24, 2007
ISL59451 Typical Performance Curves
NORMALIZED MAGNITUDE (dB) 5 VIN = 100mVP-P 0 CL = 7.4pF -5 CL = 0.6pF -10 -15 -20 0.1k 1M 10M 100M 1G 10G FREQUENCY (Hz) CL = 5.3pF CL = 2.1pF CL = 12.6pF
VCC = +5V, RL = 150 to GND, TA = +25C, unless otherwise specified.
NORMALIZED MAGNITUDE (dB) 5 VIN = 700mVP-P 0 -5 CL = 0.6pF -10 CL = 2.1pF -15 -20 0.1k CL = 5.3pF CL = 7.4pF CL = 12.6pF
1M
10M
100M
1G
10G
FREQUENCY (Hz)
FIGURE 1. SMALL SIGNAL GAIN vs FREQUENCY vs CL INTO 150 LOAD, GAIN = 1
FIGURE 2. LARGE SIGNAL GAIN vs FREQUENCY vs CL INTO 150 LOAD, GAIN = 1
5 NORMALIZED MAGNITUDE (dB) NORMALIZED MAGNITUDE (dB) VIN = 100mVP-P 0 CL = 7.4pF -5 -10 -15 -20 0.1k 1M 10M 100M 1G 10G FREQUENCY (Hz) CL = 0.6pF CL = 5.3pF CL = 2.1pF CL = 12.6pF
5 VIN = 700mVP-P 0 CL = 7.4pF -5 -10 -15 -20 0.1k CL = 0.6pF CL = 5.3pF CL = 12.6pF
CL = 2.1pF 1M 10M 100M 1G 10G
FREQUENCY (Hz)
FIGURE 3. SMALL SIGNAL GAIN vs FREQUENCY vs CL INTO 150 LOAD, GAIN = 2
FIGURE 4. LARGE SIGNAL GAIN vs FREQUENCY vs CL INTO 150 LOAD, GAIN = 2
NORMALIZED MAGNITUDE (dB)
NORMALIZED MAGNITUDE (dB)
1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 0.1k 1M CL = 2.1pF CL = 0.6pF 10M 100M 1G 10G CL = 5.3pF VIN = 100mVP-P CL = 7.4pF
1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 0.1k 1M CL = 0.6pF 10M 100M 1G 10G CL = 2.1pF CL = 5.3pF VIN = 700mVP-P CL = 7.4pF
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 5. SMALL SIGNAL GAIN FLATNESS, GAIN = 1
FIGURE 6. LARGE SIGNAL GAIN FLATNESS, GAIN = 1
6
FN6253.0 September 24, 2007
ISL59451 Typical Performance Curves
NORMALIZED MAGNITUDE (dB) 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 0.1k 1M CL = 2.1pF CL = 0.6pF 10M 100M 1G 10G CL = 5.3pF VIN = 100mVP-P CL = 7.4pF
VCC = +5V, RL = 150 to GND, TA = +25C, unless otherwise specified. (Continued)
NORMALIZED MAGNITUDE (dB) 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 0.1k 1M CL = 2.1pF CL = 0.6pF 10M 100M FREQUENCY (MHz) 1G 10G CL = 5.3pF VIN = 700mVP-P CL = 7.4pF
FREQUENCY (MHz)
FIGURE 7. SMALL SIGNAL GAIN FLATNESS, GAIN = 2
FIGURE 8. LARGE SIGNAL GAIN FLATNESS, GAIN = 2
48 46 CURRENT (mA) 44 42 40 38 36 4.5 CLAMP = LOW REF_G = REF_RB = 0.5V INPUTS FLOATING, NO LOAD CLAMP = HIGH REF_G = REF_RB = 0.5V INPUTS = 1.6V, NO LOAD CURRENT (mA)
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
5.4
5.5
3.00 2.95 2.90 2.85 2.80 2.75 2.70 2.65 2.60 2.55 2.50 2.45 4.5
HIZ = HIGH
4.6
4.7
4.8
VOLTAGE (V)
4.9 5.0 5.1 VOLTAGE (V)
5.2
5.3
5.4
5.5
FIGURE 9. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 10. DISABLED SUPPLY CURRENT vs SUPPLY VOLTAGE
23 22
2500 2000
IMPEDANCE ()
21 20 19 18 17 16 0.1k GAIN 1 1M 10M 100M GAIN 2
IMPEDANCE ()
1500 1000 500 0 0.1k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 11. ZOUT vs FREQUENCY - ENABLED
FIGURE 12. ZOUT vs FREQUENCY - DISABLED
7
FN6253.0 September 24, 2007
ISL59451 Typical Performance Curves
0 -10 -20 -30 GAIN 2 -40 -50 GAIN 1 -60 0.001k 0.01k 0.1k 1M FREQUENCY (Hz) 10M 100M
-80 -90 0.1k 1M 10M 100M 1G 10G
VCC = +5V, RL = 150 to GND, TA = +25C, unless otherwise specified. (Continued)
0 -10 -20
VAC = 100mVP-P CROSSTALK (dB)
GREEN INPUT DRIVEN 100mVP-P TO ROUT/GOUT
TO
PSRR (dB)
-30 -40 -50 -60 -70
GAIN 2
GAIN 1
FREQUENCY (Hz)
FIGURE 13. PSRR vs FREQUENCY
FIGURE 14. ACTIVE CHANNEL CROSSTALK
0 1 INPUT DRIVEN TO 100mVP-P TO -20 ANY DE-SELECTED OUTPUT ISOLATION (dB) -40 -60 -80 GAIN 2 -100 -120 0.1k ISOLATION (dB)
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 1M 10M 100M FREQUENCY (MHz) 1G 10G -100 0.1k 1M 10M 100M FREQUENCY (Hz) 1G 10G HIZ = HIGH 1 INPUT DRIVEN TO 100mVP-P TO ANY OUTPUT
GAIN 1
FIGURE 15. DE-SELECTED CHANNEL OFF ISOLATION
FIGURE 16. DISABLED ISOLATION
450 400 VOLTAGE NOISE (nVHz) 350 300 250 200 150 100 50 0 10 100 1k FREQUENCY (Hz) 10k DIFF GAIN (%)
0.0030 0.0025 0.0020 0.0015 0.0010 0.0005 0 -0.0005 VAC = 40mVP-P
-0.0010 0.30 0.47 0.64 0.81 0.98 1.15 1.32 1.49 1.66 1.83 2.00 OUTPUT DC LEVEL (V)
FIGURE 17. INPUT REFERRED NOISE vs FREQUENCY
FIGURE 18. DIFFERENTIAL GAIN; fO = 3.58MHz, RL = 150
8
FN6253.0 September 24, 2007
ISL59451 Typical Performance Curves
0.06 0.04 0.02 PHASE () 0 -0.02 -0.04 -0.06 -0.08 VAC = 40mVP-P 0.81 0.98 1.15 1.32 1.49 1.66 1.83 2.00 GAIN 1 CLAMP RSOURCE = 25 CCOUPLING = 0.1F OUTPUT GAIN 1
VCC = +5V, RL = 150 to GND, TA = +25C, unless otherwise specified. (Continued)
REF_G = REF_RB = 180mV INIT CONDITION: CLAMP = LOGIC HIGH (OFF) for 10ms
CLAMP = 1V/DIV OUTPUT = 60mV/DIV TIMEBASE = 20s
-0.10 0.30 0.47 0.64
OUTPUT DC LEVEL (V)
FIGURE 19. DIFFERENTIAL PHASE; fO = 3.58MHz, RL = 150
FIGURE 20. DC RESTORE SETTLING TIME
INPUT = NTSC VIDEO + SQUARE WAVE
INPUT = NTSC VIDEO + SQUARE WAVE
OUTPUT CLAMP = NTSC HSYNC VERTICAL = 300mV/DIV TIMEBASE = 2ms/DIV CLAMP = NTSC HSYNC
OUTPUT VERTICAL = 300mV/DIV TIMEBASE = 2ms/DIV
FIGURE 21. RESPONSE TO +300mV DC STEP ON INPUT (SEE FIGURE 36)
FIGURE 22. RESPONSE TO -300mV DC STEP ON INPUT (SEE FIGURE 36)
INPUT
INPUT
OUTPUT
OUTPUT INPUT = 500mV/DIV OUTPUT = 500mV/DIV TIMEBASE = 5ns/DIV
INPUT = 500mV/DIV OUTPUT = 1V/DIV TIMEBASE = 5ns/DIV
FIGURE 23. PULSE RESPONSE, GAIN = 1
FIGURE 24. PULSE RESPONSE, GAIN = 2
9
FN6253.0 September 24, 2007
ISL59451 Typical Performance Curves
VCC = +5V, RL = 150 to GND, TA = +25C, unless otherwise specified. (Continued)
HIZ
HIZ = 1V/DIV OUTPUT = 200mV/DIV TIMEBASE = 100ns/DIV
HIZ
HIZ = 1V/DIV OUTPUT = 200mV/DIV TIMEBASE = 100ns/DIV GAIN = 1
OUTPUT
OUTPUT
FIGURE 25. HIZ SWITCHING GLITCH, VIN = 0V, GAIN = 1
FIGURE 26. HIZ SWITCHING GLITCH, VIN = 0V, GAIN = 2
HIZ = 1V/DIV OUTPUT = 200mV/DIV TIMEBASE = 100ns/DIV S1, S0 HIZ
S1, S0 = 1V/DIV OUTPUT = 500mV/DIV TIMEBASE = 5ns/DIV
OUTPUT tHIZ-H-L OUTPUT tHIZ-L-H tSW-L-H tSW-H-L
FIGURE 27. HIZ SWITCH TIMING, VIN = 1VDC
FIGURE 28. CHANNEL TO CHANNEL SWITCHING TIME, VIN = 1VDC
NORMALIZED MAGNITUDE (dB)
5 VIN = 100mVP-P 0 CL = 7.4pF -5 -10 -15 -20 0.1k CL = 0.6pF NORMALIZED MAGNITUDE (dB)
5 VIN = 700mVP-P 0 -5 -10 -15 -20 0.1k CL = 0.6pF
CL = 7.4pF
1M
10M 100M FREQUENCY (Hz)
1G
10G
1M
10M 100M FREQUENCY (Hz)
1G
10G
FIGURE 29. SMALL SIGNAL GAIN vs FREQUENCY vs CL INTO 75 LOAD, GAIN = 1
FIGURE 30. LARGE SIGNAL GAIN vs FREQUENCY vs CL INTO 75 LOAD, GAIN = 2
10
FN6253.0 September 24, 2007
ISL59451 Typical Performance Curves
NORMALIZED MAGNITUDE (dB) 5 VIN = 100mVP-P 0 -5 CL = 0.6pF -10 -15 -20 0.1k CL = 7.4pF
VCC = +5V, RL = 150 to GND, TA = +25C, unless otherwise specified. (Continued)
NORMALIZED MAGNITUDE (dB) 5 VIN = 700mVP-P 0 -5 CL = 0.6pF -10 -15 -20 0.1k CL = 7.4pF
1M
10M 100M FREQUENCY (Hz)
1G
10G
1M
10M 100M FREQUENCY (Hz)
1G
10G
FIGURE 31. SMALL SIGNAL GAIN vs FREQUENCY vs CL INTO 75 LOAD, GAIN = 2
FIGURE 32. LARGE SIGNAL GAIN vs FREQUENCY vs CL INTO 75 LOAD, GAIN = 2
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD - QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 3.0 2.857W POWER DISSIPATION (W) QFN32 JA = 35C/W POWER DISSIPATION (W) 2.5 2.0 1.5 1.0 0.5 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) 1.0 0.8 1.2
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD
758mW 0.6 0.4 0.2 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) QFN32 JA = 125C/W
FIGURE 33. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 34. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
11
FN6253.0 September 24, 2007
ISL59451 Functional Block Diagram
S0 S1 CX1 R0/G0/B0 CX1 R1/G1/B1 1.6V + S1 4k A1 ROUT GOUT BOUT AV2
TABLE 1. CHANNEL SELECT LOGIC TABLE S1
0 0 1 1 X
S0
0 1 0 1 X
HIZ
0 0 0 0 1
OUTPUT
R0, G0, B0 R1, G1, B1 R2, G2, B2 R3, G3, B3 High Impedance, Inputs Disconnected
CX1 R2/G2/B2 CX1 R3/G3/B3
V1
A2 + -
40pF
REF_G OR REF_RB
CLAMP
GND
Pin Descriptions
ISL59451 (32 LD QFN)
1 2 3 4, 6, 10, 17, 22, 27, 32 5, 20, 28 7 8 9 11 12 13 14 15 16 18 19 21 23 24 25
PIN NAME
R1 B1 G1 GND V+ R2 B2 G2 R3 B3 G3 S1 S0 CLAMP GOUT REF_G BOUT REF_RB ROUT AV2
EQUIVALENT CIRCUIT
Circuit 1 Circuit 1 Circuit 1 Circuit 4 Circuit 4 Circuit 1 Circuit 1 Circuit 1 Circuit 1 Circuit 1 Circuit 1 Circuit 2 Circuit 2 Circuit 2 Circuit 3 Channel 1 Red/Pr/Chroma Input Channel 1 Blue/Pb/Chroma Input Channel 1 Green/Luma Input Ground
DESCRIPTION
Positive Supply. Bypass to GND with 0.01F and 1nF capacitors. Channel 2 Red/Pr/Chroma Input Channel 2 Blue/Pb/Chroma Input Channel 2 Green/Luma Input Channel 3 Red/Pr/Chroma Input Channel 3 Blue/Pb/Chroma Input Channel 3 Green/Luma Input Channel selection pin MSB (binary logic code). This pin does not have internal pull-up or pull-down resistors. Channel selection pin. LSB (binary logic code). This pin does not have internal pull-up or pull-down resistors. Clamp/Store Logic Input. Logic `0' selects the clamp DC restore state, logic `1' selects the hold state. This pin does not have internal pull-up or pull-down resistors. Green/Luma Output Green/Luma Reference. Green/Luma channel offset by this voltage during DC restore state. Reference voltage range is 0 to +3.0V.
Circuit 3
Blue Output Red and Blue Reference. Red and blue channels offset by this voltage during DC restore state. Reference voltage range is 0 to +3.0V.
Circuit 3 Circuit 2
Red Output Gain Set. Set to logic high for gain of x2 (+6dB), or set to logic low for a gain of x1 (+0dB). If left floating, an internal pull-down resistor pulls this pin low (300k pull-down).
12
FN6253.0 September 24, 2007
ISL59451 Pin Descriptions
ISL59451 (32 LD QFN)
26
(Continued) PIN NAME
HIZ
EQUIVALENT CIRCUIT
Circuit 2
DESCRIPTION
Output disable (active high). Internal pull-down resistor ensures the device will be active with no connection to this pin. A logic high puts the outputs in a high impedance state. Use this state to control logic when more than one MUX-amp share the same video output line. During high impedance state, there is a 2k pull-down present at each output. If left floating, an internal pull-down resistor pulls this pin low (300k pull-down). Channel 0 Red/Pr/Chroma Input Channel 0 Blue/Pb/Chroma Input Channel 0 Green/Luma Input Exposed Pad. Connect to GND
V+ * OUT * GND V+
29 30 31 -
R0 B0 G0 EP
V+
Circuit 1 Circuit 1 Circuit 1
IN
LOGIC PIN
GND
GND
CIRCUIT 1
CIRCUIT 2 *Not Always Present. Refer to "Pin Description"
CIRCUIT 3
V+
CAPACITIVELY COUPLED ESD CLAMP
THERMAL HEAT SINK PAD ~1M GND SUBSTRATE
GND
CIRCUIT 4
13
FN6253.0 September 24, 2007
ISL59451
ISL59451 VIN 50 OR 75 x2 *CL 2.1pF RL 150 VOUT
Application Information
General
The ISL59451 triple 4:1 MUX video driver features single +5V supply operation, high bandwidth and TTL/CMOS logic compatible gain select (AV2) of x1 (0dB) or x2 (+6dB). It also includes a DC restore function to set the blanking level of the output signal. The ISL59451 implements the video DC-restore function with a high performance gain-adjustable video amplifier and a nulling, sample-hold amplifier to establish a user defined DC reference voltage at the video amplifier output. A detailed description of the DC-restore function implemented in the ISL59451 can be found in application note AN1089, EL4089 and EL4390 DC-Restored Video Amplifier. The ISL59451 performs the same function with the exception that it is designed for single supply operation. Each of the three output channels feature DC restore functionality.
*CL Includes PCB trace capacitance
FIGURE 35A. TEST CIRCUIT WITH OPTIMAL OUTPUT LOAD
ISL59451 VIN 50 OR 75 x2
LCRIT RS
CL
CS
RL
FIGURE 35B. INTER-STAGE APPLICATION CIRCUIT
Video Amplifier Operation
(refer to "Functional Block Diagram" on page 12) The ISL59451 video amplifier (A1) is a voltage-feed, high performance video amplifier designed for +5V operation. The output stage is capable of swinging to within 15mV of the negative rail. The differential input stage contains an internal voltage reference that positions the non-inverting input DC level (V1) to ~1.6V higher than ground. This offset ensures that the amplifier input DC level is maintained within the common mode input voltage range. The amplifier non-inverting gain is given in Equation 1.
RF V OUT = ( V IN+ - 1.6V ) * 1 + ------- R G (EQ. 1)
ISL59451 VIN 50 x2
LCRIT
RS 86.6
TEST EQUIPMENT 50
118 *CL 2.1pF
*CL Includes PCB trace capacitance
FIGURE 35C. 150 TEST CIRCUIT WITH 50 LOAD
DC-Restore Amplifier
ISL59451 VIN 50 OR 75 x2 LCRIT RS TEST EQUIPMENT 50/75
(refer to "Functional Block Diagram" on page 12) The DC-restore circuit contains a voltage reference amplifier and an analog switch function that closes the DC-restore loop under control of the CLAMP logic input. The A2 amplifier output stage operates in a current-feedback mode with a source capability of 860A (Typ). A logic "0" at the CLAMP input closes switch S1, which closes the DC-restore loop. The video input AC coupling capacitor, CX1, acts as a DC hold capacitor (through the 75 termination resistor) to average the current-source output of amplifier A2. When the DC-restore loop has reached equilibrium, the DC voltage stored on CX1 will be the value required to set the voltages at A1 (VOUT) and A2 (VIN+) according to Equations 2 and 3:
V OUT (DC) = V REF (EQ. 2)
50 or 75 *CL 2.1pF
*CL Includes PCB trace capacitance
FIGURE 35D. BACKLOADED TEST CIRCUIT FOR 50/75 VIDEO CABLE APPLICATION FIGURE 35. AC TEST CIRCUITS
AC Test Circuits
Figures 35A and 35B illustrate the optimum output load for testing AC performance at 150 loads. Figure 35C illustrates how to use the optimal 150 load for a 50 cable. Figure 35D illustrates the optimum output load for 50 and 75 cable-driving.
V IN+ = V OUT (DC) + 1.6V
(EQ. 3)
14
FN6253.0 September 24, 2007
ISL59451
Therefore, if VREF is set to 0V (GND); VOUT = 15mV, and the DC voltage stored on CX1 is ~1.6V. The CX1 capacitor value is chosen from the system requirements. A typical DC-restore application using an NTSC video horizontal sync to drive the CLAMP pin will result in a 62s hold time. The typical input bias current to the video amplifier is 1.2A, so for a 62s hold time, and a 0.01F capacitor, the output voltage drift is 7.5mV in one line. The restore amplifier can provide a typical source current of 860A to charge capacitor CX1, so with a 1.2s sampling time, the output can be corrected by 36mV in each line. Using a smaller value of CX1 increases both the voltage that can be corrected, as well as the droop while being held. Likewise, using a larger value of CX1, reduces the correction and droop voltages. A sample of charging and droop rates are shown in Table 2.
TABLE 2. TABLE OF CHARGE STORAGE CAPACITOR VS DROOP CHARGING RATES (NOTE) CAP VALUE (nF)
10 33 100
AC Design Considerations
High speed current-feed amplifiers are sensitive to capacitance at the inverting input and output terminals. Capacitance at the output terminal increases gain peaking and overshoot. The AC response of the ISL59451 is optimized for a total output capacitance of 2.1pF with a load of 150 (Figure 35A). When PCB trace capacitance and component capacitance exceed 2pF, overshoot becomes strongly dependent on the input pulse amplitude and slew rate. Increasing levels of output capacitance reduce stability, resulting in increased overshoot and settling time. PC board trace length (LCRIT) should be kept to a minimum in order to minimize output capacitance. At 500MHz, trace lengths approaching 1" begin exhibiting transmission line behavior and may cause excessive ringing if controlled impedance traces are not used. Figure 35B shows the optimum inter-stage circuit when the total output trace length is less than the critical length of the highest signal frequency. As a general rule of thumb the trace lengths should be less than one-tenth of the wavelength of the highest frequency component in the signal. Equation 6 shows an approximate way to calculate LCRIT in meters.
c L CRIT ------------------------------------------10 x f MAX x R (EQ. 6)
DROOP IN 62s (mV)
7.5 2.3 0.75
CHARGE IN 1.2s (mV)
103 32.5 10.3
CHARGE IN 4s (mV)
344 103 34
c = speed of light (3 x 10^8 m/s) fMAX = maximum frequency component
IB V DROOP = ---------------------------- x ( Line Time - Sample Time ) CAP Value I CLAMP V CHARGE = ---------------------------- x ( Sample Time ) CAP Value
(EQ. 4) (EQ. 5)
R = relative dielectric of board material (e.g. FR4 = 4.2) For applications where inter-stage distances are long but pulse response is not critical, capacitor CS can be added to low values of RS to form a low-pass filter to dampen pulse overshoot. This approach avoids the need for the large gain correction required by the -6dB attenuation of the back-loaded controlled impedance interconnect. Load resistor RL is still required but can be 500 or greater, resulting in a much smaller attenuation factor. For applications where pulse response is critical and where inter-stage distances exceed LCRIT, the circuit shown in Figure 35C is recommended. Resistor RS constrains the capacitance seen by the amplifier output to the trace capacitance betweeen the output pin and the resistor. Therefore, RS should be placed as close to the ISL59451 output pin as possible. For inter-stage distances much greater than LCRIT, the back-loaded circuit shown in Figure 35D should be used with controlled impedance PCB lines, with RS and RL equal to the controlled impedance.
Figure 36 shows the test setup for measuring the DC Restore's response to an input DC step shown in Figures 21 and 22.
1Hz SQUARE WAVE 500
NTSC VIDEO 75 0.1F ISL59451 75 CLAMP OUTPUT 150
NTSC HSYNC TIMING
Control Signals
S0, S1, HIZ, CLAMP, and AV2 are binary coded, TTL/CMOS compatible control inputs. The S0, S1 pins select the inputs. All three amplifiers are switched simultaneously from their respective inputs. When HIZ is pulled high, it puts the outputs in a high-impedance state and disconnects the video inputs.
FN6253.0 September 24, 2007
FIGURE 36. DC STEP RESPONSE
15
ISL59451
CLAMP enables and disables the DC restore circuitry. For control signal rise and fall times less than 10ns, the use of termination resistors on the control lines close to the part may be necessary to prevent reflections and to minimize transients coupled to the output. See Table 1 for the S1, S0 selection states. * Match channel-to-channel analog I/O trace lengths and layout symmetry. This will minimize propagation delay mismatches. * All signal I/O lines should be routed over continuous ground planes (i.e. no split planes or PCB gaps under these lines). * Put the proper termination resistors in their optimum location as close to the device as possible. * When testing, use good quality connectors and cables, matching cable types and keeping cable lengths to a minimum. * Decouple well, using aminimum of 2 power supply decoupling capacitors (1000pF, 0.01F), placed as close to the devices as possible. Avoid vias between the capacitor and the device because vias adds unwanted inductance. Larger caps can be farther away. When vias are required in a layout, they should be routed as far away from the device as possible.
High-Impedance State
An internal pull-down resistor ensures the device will be active with no connection to the HIZ pin. The HIZ state is established within approximately 25ns by placing a logic high (>2V) on the HIZ pin. If the HIZ state is selected, the output impedance is ~2000 (Figure 6). The supply current during this state is reduced to ~3mA.
Limiting the Output Current
No output short circuit current limit exists on these parts. All applications need to limit the output current to less than 50mA. Adequate thermal heat sinking of the parts is also required.
PC Board Layout
The AC performance of this circuit depends greatly on the care taken in designing the PC board. The following are recommendations to achieve optimum high frequency performance from your PC board. * Use low inductance components, such as chip resistors and chip capacitors whenever possible. * Minimize signal trace lengths. Trace inductance and capacitance can easily limit circuit performance. Avoid sharp corners; use rounded corners when possible. Vias in the signal lines add inductance at high frequency and should be avoided. PCB traces longer than 1" begin to exhibit transmission line characteristics with signal rise/fall times of 1ns or less. To maintain frequency performance with longer traces, use striplines.
The QFN Package Requires Additional PCB Layout Rules for the Thermal Pad
The thermal pad is electrically connected to GND through the high resistance IC substrate. Its primary function is to provide heat sinking for the IC. Maximum AC performance is achieved if the thermal pad is attached to a dedicated decoupled layer in a multi-layered PC board. In cases where a dedicated layer is not possible, AC performance may be reduced at upper frequencies. * The thermal pad requirements are proportional to power dissipation and ambient temperature. A dedicated layer (oftern the ground plane) eliminates the need for individual thermal pad area. When a dedicated layer is not possible, a 1"x1" pad area is sufficient for an ISL59451 dissipating 0.5W at +50C ambient. Pad area requirements should be evaluated according to the maximum ambient temperature, the maximum supply current (including worst case signals + loads), and the thermal characteristic of the PCB.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 16
FN6253.0 September 24, 2007
ISL59451
Package Outline Drawing
L32.5x5
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 02/07
4X 3.5 5.00 A B 6 PIN 1 INDEX AREA 28X 0.50 6 PIN #1 INDEX AREA
25 24
32 1
5.00
3 .10 0 . 15
17
(4X) 0.15 16 9
8
0.10 M C A B 4 32X 0.23 - 0.05
+ 0.07
32X 0.40 0.10
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 90 0.1
C
BASE PLANE
SEATING PLANE 0.08 C
( 4. 80 TYP ) ( 3. 10 )
( 28X 0 . 5 )
SIDE VIEW
(32X 0 . 23 )
C ( 32X 0 . 60)
0 . 2 REF
5
0 . 00 MIN. 0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature.
17
FN6253.0 September 24, 2007

▲Up To Search▲

Price & Availability of ISL59451IRZ

	To Download ISL59451IRZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .